Systems and methods for comparator calibration

ABSTRACT

The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is a continuation of and claims priority to U.S.patent application Ser. No. 15/146,214 filed May 4, 2016, which is acontinuation of and claims priority to U.S. patent application Ser. No.14/935,306 filed Nov. 6, 2015 (now U.S. Pat. No. 9,356,615 issued May31, 2016), all commonly assigned and hereby incorporated by referencesfor all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH AND DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits and methodsthereof.

In data communication systems, analog and digital signals are both used.Typically, digitized signals are transferred as analog signals throughcommunication medium (e.g., modulated electrical signal through copperwires, modulated optical signal through optical links, etc.). As a partof communication process, signals are converted between digital andanalog forms. Comparators are an important aspect of signal processingand performing analog to digital conversion. For example, to performanalog-to-digital conversion (ADC), comparators are important part ofthe conversion process. In a direct-conversion ADC process, a bank ofcomparators is used to sample the input signal in parallel. Asuccessive-approximation ADC uses a comparator to successively narrow arange that contains the input voltage. In both implementations, theaccuracy of comparators is important, as it directly contributes to theaccuracy of the ADCs. To keep comparators accurate, it is needed tocalibrate the comparators.

There have been various solutions and techniques for calibratingcomparators. Unfortunately, these solutions and techniques have beeninadequate for the reasons below. Therefore, new and improved systemsand methods for comparator calibration are desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits and methodsthereof. More specifically, an embodiment of the present inventionprovides a comparator calibration loop, where an up/down counter used asa digital integrator, stores a running sum based on the output of acomparator. A Digital-to-Analog Converter (DAC) converts the running sumand generates an offset calibration voltage, which is filtered by alow-pass filter module, and the filtered offset calibration voltage isused to null-out the offset and low-frequency noise of the comparator.There are other embodiments as well.

According to an embodiment, the present invention provides a system forproviding comparator calibration. The system includes a voltage input.The system additionally includes a low pass filter module electricallycoupled to the voltage input. The low pass filter module includes afirst capacitor and a second capacitor. The first capacitor and thesecond capacitor are configured in parallel. The first capacitor ischaracterized by a first capacitance value and the second capacitorbeing characterized by a second capacitance value. The first capacitancevalue is greater than the second capacitance value. The low pass filteris configured to provide an output voltage based at least on a firstvoltage of the first capacitor. The system additionally includes a firstcalibration switch provided between the first capacitor and the secondcapacitor. The system also includes a comparator electrically coupled tothe low pass filter module and configured to generate a modificationvalue. The modification value is positive if the output voltage isgreater than 0, and the modification value is negative if the outputvoltage is 0 or less. The system additionally includes an up/downcounter used as a digital integrator, electrically coupled to thecomparator and storing an m-bit digital value. The m-bit code isincremented or decremented based on the modification value. The systemalso includes a DAC electrically coupled to an up/down counter or adigital integrator. The DAC is configured to convert n-MSBs of the m-bitvalue to a feedback voltage, n being less than or equal m. The systemfurther includes a second calibration switch provided between the secondcapacitor and the DAC.

According to another embodiment, the present invention provides a systemfor providing comparator calibration, which includes a voltage input.The system also includes a comparator electrically coupled to a low passfilter module and configured to generate a modification value. Themodification value is positive if an output voltage is greater than 0,and the modification value is negative if the output voltage is 0 orless. The system additionally includes an up/down counter used as adigital integrator, electrically coupled to the comparator and storingan m-bit digital value. The m-bit value is incremented or decrementedusing the modification value. The system further includes a DACelectrically coupled to the counter. The DAC is configured to convertthe n MSBs of the m-bit value to a feedback voltage, where n is lessthan or equal m. The system also includes a low-pass filter moduleconfigured to filter the feedback voltage to generate the outputvoltage. The low-pass filter module includes at least a first capacitorand a second capacitor. The first capacitor and the ratio between thefirst and the second capacitor is configured for removing the noiseassociated with the the feedback voltage within a noise frequency rangecharacterized by the update rate of the calibration loop and the ratiobetween the first capacitor and the second capacitor.

According to yet another embodiment, the present invention provides asystem for providing comparator calibration. The system includes a firstcomparator feedback loop, which includes a first comparator, a firstup/down counter used as a digital integrator, a DAC, and a firstlow-pass filter. The system also includes a second comparator feedbackloop, which includes a second comparator, a second counter, the DAC, anda second low-pass filter. During a first time period, the firstcomparator generates a first modification value, the first countergenerates a first calibration value, the DAC generates a firstcalibration voltage, and the first low-pass filter filters the firstcalibration voltage. During the second time period, the first comparatorcalibrates using the filtered first calibration voltage, the secondcomparator generates a second modification value, the second countergenerates a second calibration value, the DAC generates a secondcalibration voltage, and the second low-pass filter filters the secondcalibration voltage.

It is to be appreciated that the embodiments of the present inventionprovide many advantages over conventional techniques. Among otherfeatures, by eliminating the need for a high gain pre-amplifier,typically implemented by cascading multiple low gain amplifiers inconventional techniques, the total size and power consumption ofcomponents involved in calibrating a comparator is substantiallyreduced. More specifically, a comparator calibration loop according tothe embodiments of the present invention can be implemented using acounter, a coarse DAC, and a low-pass filter module, and the total sizeand power consumption of these components is less than the size andpower consumption of a high gain amplifier used in conventionalcomparator calibration mechanisms. The size and area savings aremultiplied when a single DAC is shared, by time-interleaving, amongmultiple comparator calibration loops. In addition, the comparatorcalibration process is performed outside the critical signal path of thecomparator, thereby reducing the likelihood of causing noise orinterference or slow down of the main signal path, which is crucial inhigh-speed applications. The comparator calibration systems and methodsthereof are compatible with existing systems and techniques, and canthus be readily integrated into existing and future comparator designs.In addition to reducing the amount of hardware components as explainedabove, various parameters for providing offset cancellation can beconveniently adjusted. For example, the range of correctable offset canbe adjusted by simply changing the reference voltage of the DAC.Similarly, total noise, residual offset, and the number of cycles forconvergence are characteristics that can be adjusted by changing one ormore parameters. For example, to adjust these performancecharacteristics, counter number of bits m, DAC resolution n, absolutevalue of the two capacitors, the ratio between the two capacitors, andthe update rate of the calibration loop, can be easily modified to suita specific application. There are many other benefits as well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a conventional comparatorsystem 100.

FIG. 2 is a simplified diagram illustrating a comparator systemaccording to an embodiment of the present invention.

FIG. 3 is a simplified diagram illustrating a comparator calibrationsystem according to an embodiment of the present invention.

FIG. 4 provides graphs obtained by behavioral simulations thatillustrate performance of the comparator calibration system 300 shown inFIG. 3.

FIG. 5 illustrates a time-interleaved calibration system according to anembodiment of the present invention.

FIG. 6 is a simplified timing diagram illustrating operation of acomparator calibration system according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits and methodsthereof. More specifically, an embodiment of the present inventionprovides a comparator calibration loop where an up/down counter used asa digital integrator, stores a running sum based on the output of acomparator. A DAC converts the running sum and generates a calibrationvoltage, which is filtered by a low-pass filter module, and the filteredcalibration voltage is used to counter the input offset andlow-frequency noise of the comparator. There are other embodiments aswell.

As explained above, conventional comparator offset calibration methodsdepend on pre-amplifiers with high DC gain which makes them inadequatefor integrated circuits implemented in modern process technologies withdeclining inherent DC gains. For a comparator to function properly, itis often necessary to calibrate the comparator, so that the comparatorhas an accurate reference value to compare to. To achieve calibration, acomparator typically includes an auto-zero function. For example, FIG. 1is a simplified diagram illustrating a conventional comparator system100. For illustration purposes, the comparator use cases throughout thisdisclosure are shown along with a successive-approximation-register(SAR) ADC and are merely used as an example. Comparators can be usedwith other ADC architectures or other general applications where analogcomparison is required. The comparator system 100 receives analog inputvoltage from Vin 102, which is to be compared against a referencevoltage Vref 108 by the comparator 103. For illustration purposes thecomparator output 103 is connected to asuccessive-approximation-register (SAR) logic 104, which is used toperform analog to digital conversation (ADC) operation. While comparator103, implemented in conjunction with other components, is shown in FIG.1 to be used for ADC operations, it is to be understood that thecomparator 103 can be used for other functionalities as well.

The comparator system 100 has an “auto-zero” function, which refers toits ability to null-out (or “zero”) the net errors of the comparator 103at its input. Among other things, the “auto zero” function is animportant aspect of the comparator system; the offset is to becalibrated in order for the comparator to work accurately. For example,the input-referred offset (Vos) of an auto-zero system (i.e. inputseries cancellation) is Vos/(1+A). It is to be understood that Vos is aproperty of the amplifier 101. The system 100 operates in an auto-zerophase and a comparison phase. During the auto-zero phase the inputvoltage to the comparator 102 gets sampled over the bottom plate of thesampling capacitor 106 by switch 107 whilst an estimate of theun-calibrated comparator offset 105 gets sampled over the top plate ofthe sampling capacitor by switch 108. During the “auto-zero” phase, thevoltage across the sampling capacitor due to the un-calibratedcomparator offset Vos can be described asVcap=−Vos*A/(1+A)  Equation 1:This is merely an estimate of the actual Vos where the accuracy of theestimate improves only by increasing the gain value A.

During the “comparison” phase when the switch 109 is closed the voltageat the output of the amplifier 101 can be described asVout=A[(Vin−Vref)−Vos/(1+A)]  Equation 2:

According to the above the ideal portion of the comparator operation isrepresented by the difference voltage (Vin−Vref) and the non-idealportion is represented by a residual offset Vres=Vos/(1+A) which is anattenuated version of the original input referred offset Vos 105. Forthe scheme illustrated in FIG. 1, the residual offset “Vres” is afunction of the amplifier gain “A” and the Vos. An important objectiveis to minimize the residual offset Vres, and based on Equation 2, alarger amplifier gain (“A”) translates to samller residualinput-referred offset. Thus, for the error term “Vres” to be small, theamplification of the amplifier 101 needs to be high.

In electrical circuits utilizing discrete components, or in integratedcircuits implemented in older process nodes with large device gains,providing amplification is relatively simple by utilizing a high-gainamplifier. However, providing a high gain amplifier is challenging inintegrated circuits (IC) that are manufactured in the nanometer scale.For example, leading microprocessors are now manufactured using 14 nmand 20 nm processes, and IC components such as CMOS logic oftenmanufactured using processes that are 40 nm or less. Using thesenanometer scale processes, implementing high gain amplifier typicallyrequires cascading many amplifiers to achieve the requiredamplification. Unfortunately, there are a few disadvantages associatedwith having high gain amplifiers. High gain amplifiers, in IC design,typically needs to be implemented using multi-stage or “cascaded”amplifiers. The arrangement of cascading multiple low-gain amplifiers ismerely intended to achieve high overall gain without significantslowdown of the signal path, which could be the case with a single-stagehigh-gain amplifier. Nonetheless, this practice leads to increasedoverall power consumption and chip area. Moreover, using multipleamplifiers means introducing additional delays and timing issues. It isworth mentioning the single-stage high-gain amplifiers are typicallycharacterized by their high output impedance, which in combination withthe load capacitance creates a large time-constant, directly translatingto lower speeds. As a result, implementing a high gain amplifier or theequivalent thereof is expensive and sometimes impractical (e.g. speedpenalty unacceptable or large chip area unavailable for the multi-stagehigh gain amplifier). In addition, with the amplifier 101 positioned inthe critical path of the comparator system 100, there could be signaldegradation.

It is thus to be appreciated that embodiments of the present inventionprovide a calibration scheme for comparators. More specifically, byusing digital integrator and digital-analog-converter (DAC), among othercomponents, embodiments of the present invention provide a calibrationscheme that allows calibration to be carried out outside the criticalsignal path of the comparator and does not require a high-gainamplifier. The details of the comparator calibration systems accordingto embodiments of the present invention are provided below.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

FIG. 2 is a simplified diagram illustrating a comparator systemaccording to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. A comparator system 200receives an input at Vin 202. For example, the input received at the Vin202 is an analog waveform, which is to be converted to a digital signal.The comparator system 200 includes a low-pass filter module 250. Thelow-pass filter module 250 includes capacitor 251 and capacitor 252. Thecapacitor 252, as a part of the calibration process, holds calibrationoffset value needed for the system. In various implementations, thecapacitance C_(AZ2) of the capacitor 251 is much greater thancapacitance C_(AZ1) of the capacitor 252. For example, in certainimplementations, C_(AZ2) can be 100 times larger than C_(AZ1).Additionally, the low-pass filter module 250 includes switch 253 andswitch 254. Operating the switch 253 determines whether the calibrationvalue from the DAC is to be loaded to the capacitor 252. For example,the calibration value from the DAC is effectively the calibrationvoltage that can be later used to calibrate the comparator module.Operating the switch 254 determines whether the calibration voltage ofthe capacitor 252 is used to calibrate the comparator 240. If thecalibration voltage is to be used, the calibration is performed with Vos205. As an example, Vos 205 represents the equivalent input-referredoffset of the comparator 240. Because DAC 220 has finite resolution, itcan introduce quantization noise directly to the comparator input. Thelow-pass filter module 250 is configured to attenuate the errorsintroduced by the quantization effects at DAC 220. In other words, thelow-pass filter 250 smoothes out the instantaneous jumps at DAC 220output and gradually settles to the average value represented by the DACoutput levels. More specifically, in the low-pass filter 250 thecapacitor 251 holds the “auto-zero” voltage, thereby providing an offsetnulling function. The size of the capacitor 251 is related to thecharacteristics of the DAC 220 such as resolution and update rate. Inaddition to providing calibration voltage at a predetermined time,

It is to be appreciated that the comparator 240 and its output can beused for different applications. As shown in FIG. 2, the output of thecomparator 240 is, as example, used by the processing device 230, whichcan be used for performing ADC operations. For example, the processingdevice 230 can be the control logic of a SAR ADC, encoding logic of aflash ADC, or others. Depending on the application, the comparator 240may also be used as a part a null detector, a zero-crossing detector, arelaxation oscillator, a level shifter, or a window detector. Thecomparator 240 is calibrated without using a high-gain amplifier in itscritical path through which it receives the input voltage. The output ofthe comparator 240 as shown is used by the processing device 230.

In addition to performing its function as a comparator, the comparator240 also provides a value that is used in a calibration feedback loopcomprising the digital integrator module 210, DAC 220, and low-passfilter module 250. More specifically, the digital integrator module 210generates a digital value using the logic “0” or “1” output of thecomparator 240. For example, the integrator output value stored atregister 213 is a running sum based on the comparator output. Theregister 213 value is processed by the DAC 220 to generate the analogcalibration voltage needed. The DAC 220 resolution and update rate arerelated to the capacitances of capacitors 251 and 252 and the ratiothereof. The calibration voltage is stored by the capacitors of thelow-pass filter and used to calibrate the comparator 240.

The digital integrator module 210 is implemented with a moderateresolution (e.g., 10-bits) according to an embodiment of the presentinvention, and its running sum tracks and digitally quantifies thepolarity and magnitude of the comparator offset. The integrator 210input is connected to the comparator 240 output and based on thecomparator decision during an “auto-zero” phase (e.g. while φ₁ andφ_(1 e)switches are closed), the polarity of the comparator offset isdetected and its magnitude can be quantified and tracked over the longterm.

More specifically, to keep the comparator calibrated, the digitalintegrator 210 accumulates the output values of the comparator 240. Morespecifically, the output of the comparator 240 is generated by comparingthe equivalent input offset of the comparator represented by the voltagesource Vos 205 and the voltage across capacitor 251. If the differenceof Vos 205 and voltage across capacitor 251 were larger than zero, thecomparator 240 outputs a value of “1”, which means that the voltageacross capacitor 251 at certain point needs to be increased to counterthe offset voltage; on the other hand, if the difference had a negativevoltage (i.e., below zero), the comparator 240 outputs a value of “−1”,which means that the voltage across capacitor 251 at certain pointsneeds to be decreased. By using the digital integrator module 210 andthe DAC 220 in the calibration feedback loop, the Vos 205 offset voltageis calibrated over time. Effectively, the digital integrator 210 storesa running sum based on the Vos over time and reflecting the offsetvoltage over time.

It is to be appreciated that the digital integrator 210 consists of aninput scaling 211 with attenuation factor of β<1, the digital summer 212and output register 213. In the embodiment 200 shown in FIG. 2, theintegrator 210, the DAC 220, the low-pass filter 250 and the comparator240 constitute a sampled-data(discrete-time) negative feedback loopwhich is updated at a frequency less than or equal to the comparatorclock frequency. It is also to be appreciated that the scaling factor βcan be optimized to meet stability and convergence-time requirements ofthe feedback loop. For example, the scale factor β>1 makes thecalibration loop unstable. On the other hand if β is chosen too small itcan prolong the convergence-time of the loop.

Depending on the specific embodiment, the β scaling factor 211 ofdigital integrator 210 can be implemented in various ways. A simple wayof implementing an attenuation factor, with β<1, is by “shift to theright” operation. For example, scaling factor 211 as shown in

FIG. 2 is merely a function block, not an actual circuit, whenimplemented by “shift” operation. To “shift” the integrator value,digital integrator 210 can simply send a selected number of mostsignificant bits (MSB) to the DAC 220. For example, in an exemplaryimplementation, digital integrator 210 has an m-bit register, whichaccumulates the output of the comparator 240 and stores the result as anm-bit digital value. The output of the integrator 210 that is connectedto the DAC is an n-bit value, where n is less than m, and differencebetween m and n is the shift factor needed for β=2^((n−m)), while n<m.For example, an exemplary design, based on FIG. 2, uses a 10-bitintegrator (e.g. m=10) where only the 6 MSBs (e.g. n=6) are tied to theDAC. Effectively, the scaling factor β is 2⁻⁴ (i.e., 2₆₋₁₀). Thetruncation of them m−n LSBs effectively weights the 1-bit input to theintegrator by a factor of 2_(n−m). In this example the n MSB bits of theintegrator are updated at most once per 16 clock cycles. In other words,if the output of the comparator were kept high for 16 consecutive clockcycles, the DAC 210 would increment by 1. Depending on the specificimplementation, the shift factor β can be selected based on the desiredresolution, dynamic noise performance, calibration convergence time,characteristics of various components (such as capacitor size,capacitance ratio . . . ), and/or other factors.

The integrator module 210 can be implemented by a digital accumulator orby a simple up/down counter. It is to be appreciated that the integrator210 may be implemented in other ways as well. For example, in FIG. 3 theup/down counter 311 is used to implement the digital integrator 210 (ofFIG. 2). The digital integrator 210, as shown in FIG. 2, is triggered atthe falling edge of the clock, when the data value of the comparatoroutput is expected to settle. For example, when the clock is “on” orΦ₁=1, the DAC 220 generates a calibration value using the output fromthe integrator 210, while register 213 keeps the output value steadyduring this period. During the same time, the DAC 220 output is beingsampled onto the low-pass filter capacitor 252 (C_(AZ1)). The digitalintegrator value is updated at the falling edge of the clock.Subsequently, when the clock is “off” or Φ₁=0, the DAC 220 prepares thenext analog value to be sampled over capacitor 252 (C_(AZ1)).

In order to speed up the convergence time of the calibration loop, thedigital integrator 210, at the very start of its operation, initiallystores a midpoint value. That is, when the system 200 initializes, theregister 213 of integrator 210 will be reset to a midpoint value. Forexample, if the register 213 has a range of 0 to 2_(m), the midpointvalue is 2^(m−1). On the other hand, when using a signed logic format,digital integrator 210 (and register 213) assumes a range of −2^(m−1) to2^(m−1), with the midpoint value set to 0 at the start-up.

The DAC 220 converts the calibration code received from digitalintegrator 210 to a calibration voltage. As explained above, the DAC 220is an n-bits DAC and it only converts the n MSBs of the m-bit digitalintegrator 210. Typically, a DAC module is often an expensive component.By reducing the number of bits that DAC converts, a less expensive DAC(e.g., DAC converting fewer bits into analog signal) can be used. Inaddition, the DAC 220 can be shared (see FIGS. 5 and 6) among multiplecomparator calibration loops. As mentioned above, the low-pass filter250 attenuates the quantization noise of the DAC 220. According tovarious implementations, the DAC 220 generates a coarse analogrepresentation, which has opposite polarity and approximately equalmagnitude (with rounding off by LSBs at the integrator) to thecomparator offset based on the running sum produced by digitalintegrator 210. One of the implementation objectives is to reduce theamount of dynamic noise created by the control loop itself, and to do sothe DAC quantization needs to be maintained at a sufficiently low level(negligible compared to comparator self electronic noise).

The calibration voltage generated by the DAC 220 is provided to thelow-pass filter module 250, which uses the calibration voltage to cancelout the comparator offset error Vos 205. The low-pass filter moduleadditionally attenuates quantization noise of the DAC 220. It is to beappreciated that comparator calibration system 200 in FIG. 2 creates adynamic negative feedback loop with a high-pass transfer function withrespect to comparator input terminals, that attenuates the low frequencynoise components attributed to comparator DC offset and flicker noise.The corner frequency of attenuation depends on the update rate of theloop as well as capacitor ratio C_(AZ2)/C_(AZ1) in the low-pass filter250. The update rate is associated with the bandwidth of low-frequencyflicker (1/f) noise tracking. More specifically, increasing the updaterate causes an increase in the tracking bandwidth of the low-frequencynoise.

For most applications, it is desirable to keep the offset cancellationvalue stable. For example, keeping the ratio C_(AZ2)/C_(AZ1) high (e.g.,100 or larger) can attenuate most of the dynamic errors contributed bythe calibration loop and keep the feedback value very stable. On theother hand, the larger capacitive ratio causes a reduction in thetracking bandwidth of the comparator flicker noise. Hence in theproposed comparator calibration system there is a trade-off betweenflicker noise tracking bandwidth and DAC 220 quantization noisefiltering. An optimal design can be achieved when the two noise sourcescontribute equally to the residual error. For example in a givenimplementation with 6-bit calibration DAC a capacitor ratio ofC_(AZ2)/C_(AZ1)=8 achieves such a trade-off. Depending on the processtechnology used, in certain implementations C_(AZ1) cannot be too small,and as a result C_(AZ2) has to be large enough to keep the ratio high.

FIG. 3 is a simplified diagram illustrating a comparator calibrationsystem according to an embodiment of the invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, in the system300 illustrated in FIG. 3 the low-pass filter 313 resembles the low-passfilter 250 in FIG. 2 and the up/down counter 311 resembles the digitalintegrator 210 in FIG. 2. In the system 300 shown in FIG. 3 the inputsignal is received at Vin 301, which is processed by the comparator 303during the comparison phase when the sampling clock is “off” or Φ1=0.The inputs of the comparator 303 are coupled to the analog input Vin 301through sampling capacitor 302 and coupled to the calibration feedbacksystem 310 through voltage stored in hold capacitor C_(AZ2) 314. Thevoltage source Vos 304 is used to model the equivalent input referredoffset of the comparator 303. The calibration feedback system 310includes the up/down counter 311 used as a digital integrator, a DAC312, and a low-pass filter module 313 comprising the sampling capacitorC_(AZ1) 315 and hold capacitor C_(AZ2) 314.

FIG. 4 provides graphs obtained by behavioral simulations thatillustrate performance of the comparator calibration system 300 shown inFIG. 3. The simulated system involves an offset calibration loopcomprising a low resolution 6-bit DAC and a moderate resolution 10-bitcounter. The counter is characterized by a shift factor of 2⁻⁴. As shownin graph 4D of FIG. 4, the simulated comparator offset range is ±60 mV,where the residual offset is reduced to ±200 μV (worst case) orattenuated by a factor of 300 in roughly 1000 cycles as shown in graph4A of FIG. 4. The residual offset is approximately 40 times smaller thanthe LSB of the ADC. It is to be appreciated that this level of offsetreduction is useful for a wide range of applications. As shown in graph4A, a comparator calibration system operated over 4000 cycles, with aneffective comparator input noise of about 1.9 mVrms. Initially, thecomparator input offset was about −60 mV which is quickly corrected toabout 0. The offset voltage was able to stabilize around −98.5 μV. Theinformation is shown in graph 4B shows the histogram of comparator inputvoltage. More specifically, graph 4B shows a histogram of the voltage atthe comparator input at each point in graph 4A after the calibration hasconverged (i.e., after 1000 cycles), where the standard deviation is 1.9mV with a mean of −98 uV. The intrinsic noise of the comparator beforecalibration was 1.88 mVrms. The increase in noise from 1.88 mVrms to 1.9mVrms after calibration is contributed by 280 μVrms dynamic noise fromthe calibration loop. Graph 4C shows the total RMS noise versuscomparator offset Vos. As can be seen in graph 4C, the total noise canvary between 1.75 mV to 1.95 mV depending on the intrinsic(un-calibrated) offset of the comparator. Graph 4D shows therelationship between the residual (post calibration) offset and theintrinsic offset voltage Vos. As shown in graph 4D the residual offsetalso varies between −200 uV and 200 uV depending on the pre calibratedoffset Vos.

As can be seen from FIG. 4, the embodiments of the present inventionprovide many performance advantages. In addition to reducing the amountof hardware components as explained above, various parameters forproviding offset can be conveniently adjusted. For example, the range ofcorrectable offset can be adjusted. Similarly, total noise, residualoffset, and the number of cycles for converging is one of thecharacteristics that can be adjusted by changing one or more parameters.For example, to adjust these performance characteristics, counter shiftvalue, counter resolution, DAC resolution, and capacitor values can beeasily modified to suit the specific applications.

FIG. 5 illustrates a time-interleaved calibration system 500 accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. As shown in FIG. 5, four comparators utilize a singleDAC to perform a coarse estimate of each respective comparator offset.More specifically, comparators 511-514 utilize the DAC 520 andrespectively use counters 501-504 for calibrating offset voltage. Forexample, the counter 501, the DAC 520, and the comparator 511 togetherform a comparator calibration feedback loop, similar to the system 200shown in FIG. 2. Since the DAC 520 is not needed for calibrating thecomparator 511 at the all times, comparators 512-514 use the DAC 520 attheir respective pre-assigned time slots when the comparator 511 isutilizing the DAC 520 for calibration. In short, the DAC 520 istime-interleaved between the four comparators 511-514. It is to beappreciated that by interleaving the DAC 520, the number of hardwarecomponents is substantially reduced, which translates to lowered costand size. As an example, there can be multiple comparators, each withits own counters and other components, to share the DAC for providingcorrection voltage.

FIG. 6 is a simplified timing diagram illustrating operation of acomparator calibration system according to an embodiment of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications. For example,Φ₁ is associated with the calibration phase of the comparator system 501shown in FIG. 5. More specifically when Φ₁ is on at time 605, the outputof the counter 501 in FIG. 5 is connected to the DAC 520, and at thesame time the DAC output voltage is sampled to the low-pass filterassociated with comparator 511. Similarly, when the Φ₂ is on, thecounter 502 gets connected to the DAC, and DAC output voltage getssampled onto the low-pass filter associated with comparator 512. Sincethere are four comparator calibration systems, the Φ₁ is not on untilfour phases later at time 606. For example, the four phases 601-604respectively correspond to comparators 511-514 regarding the calibrationthereof.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A system for providing comparator calibration,the system comprising: a voltage input; a low pass filter moduleelectrically coupled to the voltage input and comprising a firstcapacitor, a second capacitor, a first calibration switch, and a secondcalibration switch, the first capacitor and the second capacitor beingconfigured in parallel through the first calibration switch, the firstcapacitor being characterized by a first capacitance value and thesecond capacitor being characterized by a second capacitance value, thefirst capacitance value being greater than or equal to the secondcapacitance value, the low pass filter being configured to provide anoutput voltage based at least on a first voltage of the first capacitor;a comparator electrically coupled to the low pass filter module andconfigured to generate a modification value, the modification valuebeing positive if the output voltage is greater than 0, and themodification value being negative if the output voltage is 0 or less; afeedback loop circuit including a digital integrator and a DAC, thedigital integrator being electrically coupled to the comparator andstoring an m-bits value, the m-bits value being updated using themodification value, the DAC being electrically coupled between thedigital integrator and the second calibration switch and configured toconvert the n MSBs of the m-bits value to a calibration voltage, n beingless than or equal to m.
 2. The system of claim 1 wherein the feedbackvoltage is associated with an opposite polarity relative to a comparatorintrinsic offset value.
 3. The system of claim 1 wherein the secondcalibration switch is closed at a predetermined rate.
 4. The system ofclaim 1 wherein the m-bits value is a running sum based on thecomparator output.
 5. The system of claim 1 wherein the digitalintegrator is initialized with a midpoint value.
 6. The system of claim1 wherein the voltage input is associated with an intrinsic offsetvoltage of the comparator.
 7. The system of claim 6 wherein: themodification value is +1 if the voltage input is greater than adifference between the calibration voltage and the intrinsic offsetvoltage and the modification value being negative if the voltage inputis less than the difference between the calibration voltage and theintrinsic offset voltage.
 8. The system of claim 1 wherein the low-passfilter removes high frequency noises associated with the DAC.
 9. Asystem for providing comparator calibration, the system comprising: avoltage input providing an input voltage through a sampling capacitor; acomparator electrically coupled to the voltage input to receive theinput voltage and configured to generate a modification value, themodification value being positive if a difference of an output voltagefrom a voltage source and the input voltage is greater than 0, and themodification value being negative if the difference of the outputvoltage from the voltage source and the input voltage is 0 or less; anup/down counter electrically coupled to the comparator and storing anm-bit value, the m-bit value being updated using the modification value;a DAC electrically coupled to the counter, the DAC being characterizedby a noise tracking bandwidth, the DAC being configured to convert the nMSBs of the m-bit value to a feedback voltage, n being less than orequal to m; and a low-pass filter module configured to filter thefeedback voltage to generate a calibration voltage for adjusting theoutput voltage from the voltage source, the low-pass filter modulecomprising a first capacitor and a second capacitor, the first capacitorbeing configured to removing noise associated with quantization errorsassociated with the feedback DAC.
 10. The system of claim 9 wherein them-bits value is a running-sum that is associated with the output voltagefrom the voltage source adjusted by the calibration voltage from thelow-pass filter module.
 11. A method in a system for providingcomparator calibration, wherein the system comprises a first a firstcomparator feedback loop and a second comparator feedback loop, thefirst comparator feedback loop comprising a first comparator, a firstcounter, a DAC, and a first low-pass filter; the second comparatorfeedback loop comprising a second comparator, a second counter, the DAC,and a second low-pass filter, the method comprising: during a first timeperiod, generating a first modification value by using the firstcomparator, generating a first calibration value by using the firstcounter based on an output from the first comparator, generating a firstcalibration voltage by the DAC based on the first calibration value,filtering the first calibration voltage by the first low-pass filter,and providing the first calibration voltage to the first comparator;during a second time period, generating a second modification value byusing the second comparator, generating a second calibration value byusing the second counter based on an output from the second comparator,generating a second calibration voltage by the DAC based on the secondcalibration value, filtering the second calibration voltage by thesecond low-pass filter, and providing the second calibration voltage tothe second comparator.
 12. The method of claim 11, wherein the systemfurther comprises a third comparator feedback loop and a fourthcomparator feedback loop.
 13. The method of claim 11, wherein the systemfurther comprises an SAR, the SAR being configured to use outputs of thefirst comparator and the second comparator to perform ADC operations.14. The method of claim 11, wherein the system further comprises a firstinput voltage and a second input voltage, further comprising processingthe first input voltage by using first comparator, and processing thesecond input voltage by using the second comparator.
 15. The method ofclaim 11, wherein: the system operates at a frequency Fs; the systemcomprises n comparator feedback loops, the n comparator feedback loopsincluding the first comparator feedback loop and the second comparatorfeedback loop, each of the comparators of the n comparator feedbackloops being calibrated at a frequency lower than or equal to Fs/n. 16.The method of claim 11, wherein the first low-pass filter filters a lowfrequency noise partially generated by the DAC.
 17. The method of claim15, wherein: the first counter accumulates an m-bits value; the DACconverts n MSBs of the m-bits value, n being less than or equal to m.18. The method of claim 17, wherein the DAC is shared among n feedbackloops and operates at the aggregate frequency of Fs.